x86info v1.12.  Dave Jones 2001-2003
Feedback to <davej@suse.de>.

Found 2 CPUs
MP Table:
#	APIC ID	Version	State		Family	Model	Step	Flags
#	 0	 0x14	 BSP, usable	 15	 2	 7	 0xbfebfbff
#	 1	 0x14	 AP, usable	 15	 2	 7	 0xbfebfbff

--------------------------------------------------------------------------
CPU #1
eax in: 0x00000000, eax = 00000002 ebx = 756e6547 ecx = 6c65746e edx = 49656e69
eax in: 0x00000001, eax = 00000f27 ebx = 00020809 ecx = 00000400 edx = bfebfbff
eax in: 0x00000002, eax = 665b5001 ebx = 00000000 ecx = 00000000 edx = 007b7040

eax in: 0x80000000, eax = 80000004 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000002, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000003, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000004, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000

Family: 15 Model: 2 Stepping: 7 Type: 0 Brand: 9
CPU Model: Pentium 4 (Northwood) [C1] Original OEM
Feature flags:
	Onboard FPU
	Virtual Mode Extensions
	Debugging Extensions
	Page Size Extensions
	Time Stamp Counter
	Model-Specific Registers
	Physical Address Extensions
	Machine Check Architecture
	CMPXCHG8 instruction
	Onboard APIC
	SYSENTER/SYSEXIT
	Memory Type Range Registers
	Page Global Enable
	Machine Check Architecture
	CMOV instruction
	Page Attribute Table
	36-bit PSEs
	CLFLUSH instruction
	Debug Trace Store
	ACPI via MSR
	MMX support
	FXSAVE and FXRESTORE instructions
	SSE support
	SSE2 support
	CPU self snoop
	Hyper-Threading
	Automatic clock Control
	Pending Break Enable


Pentium 4 specific MSRs:
IA32_PLATFORM_ID=0008000000000000
System bus in order queue depth=12
MSR_EBC_FREQUENCY_ID=0000000015010f00
IA32_BIOS_SIGN_ID=0000002400000000
Processor serial number is enabled
Fast strings are enabled
x87 FPU Fopcode compatability mode is disabled
Thermal monitor is enabled
Split lock is enabled

Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 64 entries.
Data TLB: 4KB or 4MB pages, fully associative, 64 entries.
L1 Data cache:
	Size: 8KB	Sectored, 4-way associative.
	line size=64 bytes.
No level 2 cache or no level 3 cache if valid 2nd level cache.
Instruction trace cache:
	Size: 12K uOps	8-way associative.
L2 unified cache:
	Size: 512KB	Sectored, 8-way associative.
	line size=64 bytes.

Number of reporting banks : 4

Number of extended MC registers : 12


Bank: 0 (0x400)
MC0CTL:    00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000
MC0STATUS: 00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000
MC0ADDR:   00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000

Bank: 1 (0x404)
MC1CTL:    00000000 00000000 00000000 00000000
           00000000 00000011 10000000 00000000
MC1STATUS: 00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000
MC1ADDR:   00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000

Bank: 2 (0x408)
MC2CTL:    00000000 00000000 00000000 00000000
           00000000 00000000 00000000 10000000
MC2STATUS: 00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000
MC2ADDR:   Couldn't read MSR 0x40a

Bank: 3 (0x40c)
MC3CTL:    00000000 00000000 00000000 00000000
           00000000 00000000 00000000 01111110
MC3STATUS: 00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000
MC3ADDR:   00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000

Number of logical processors supported within the physical package: 2

Microcode version: 0x0000000000000024

Connector type: Socket478 (PGA478 Socket)

Datasheet: http://developer.intel.com/design/pentium4/datashts/24988703.pdf
	http://developer.intel.com/design/pentium4/datashts/29864304.pdf
Errata: http://developer.intel.com/design/pentium4/specupdt/24919928.pdf

MTRR registers:
MTRRcap (0xfe): 0x0000000000000508
MTRRphysBase0 (0x200): 0x0000000000000006
MTRRphysMask0 (0x201): 0x0000000ff0000800
MTRRphysBase1 (0x202): 0x00000000f8000001
MTRRphysMask1 (0x203): 0x0000000ffc000800
MTRRphysBase2 (0x204): 0x00000000f2000001
MTRRphysMask2 (0x205): 0x0000000ffe000800
MTRRphysBase3 (0x206): 0x0000000000000000
MTRRphysMask3 (0x207): 0x0000000000000000
MTRRphysBase4 (0x208): 0x0000000000000000
MTRRphysMask4 (0x209): 0x0000000000000000
MTRRphysBase5 (0x20a): 0x0000000000000000
MTRRphysMask5 (0x20b): 0x0000000000000000
MTRRphysBase6 (0x20c): 0x0000000000000000
MTRRphysMask6 (0x20d): 0x0000000000000000
MTRRphysBase7 (0x20e): 0x0000000000000000
MTRRphysMask7 (0x20f): 0x0000000000000000
MTRRfix64K_00000 (0x250): 0x0606060606060606
MTRRfix16K_80000 (0x258): 0x0606060606060606
MTRRfix16K_A0000 (0x259): 0x0000000000000000
MTRRfix4K_C8000 (0x269): 0x0505050505050505
MTRRfix4K_D0000 0x26a: 0x0000000000000000
MTRRfix4K_D8000 0x26b: 0x0000000000000000
MTRRfix4K_E0000 0x26c: 0x0505050505050505
MTRRfix4K_E8000 0x26d: 0x0505050505050505
MTRRfix4K_F0000 0x26e: 0x0505050505050505
MTRRfix4K_F8000 0x26f: 0x0505050505050505
MTRRdefType (0x2ff): 0x0000000000000c00


2.8Ghz processor (estimate).

--------------------------------------------------------------------------
CPU #2
eax in: 0x00000000, eax = 00000002 ebx = 756e6547 ecx = 6c65746e edx = 49656e69
eax in: 0x00000001, eax = 00000f27 ebx = 01020809 ecx = 00000400 edx = bfebfbff
eax in: 0x00000002, eax = 665b5001 ebx = 00000000 ecx = 00000000 edx = 007b7040

eax in: 0x80000000, eax = 80000004 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000002, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000003, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000004, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000

Family: 15 Model: 2 Stepping: 7 Type: 0 Brand: 9
CPU Model: Pentium 4 (Northwood) [C1] Original OEM
Feature flags:
	Onboard FPU
	Virtual Mode Extensions
	Debugging Extensions
	Page Size Extensions
	Time Stamp Counter
	Model-Specific Registers
	Physical Address Extensions
	Machine Check Architecture
	CMPXCHG8 instruction
	Onboard APIC
	SYSENTER/SYSEXIT
	Memory Type Range Registers
	Page Global Enable
	Machine Check Architecture
	CMOV instruction
	Page Attribute Table
	36-bit PSEs
	CLFLUSH instruction
	Debug Trace Store
	ACPI via MSR
	MMX support
	FXSAVE and FXRESTORE instructions
	SSE support
	SSE2 support
	CPU self snoop
	Hyper-Threading
	Automatic clock Control
	Pending Break Enable


Pentium 4 specific MSRs:
IA32_PLATFORM_ID=0008000000000000
System bus in order queue depth=12
MSR_EBC_FREQUENCY_ID=0000000015010f00
IA32_BIOS_SIGN_ID=0000002400000000
Processor serial number is enabled
Fast strings are enabled
x87 FPU Fopcode compatability mode is disabled
Thermal monitor is enabled
Split lock is enabled

Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 64 entries.
Data TLB: 4KB or 4MB pages, fully associative, 64 entries.
L1 Data cache:
	Size: 8KB	Sectored, 4-way associative.
	line size=64 bytes.
No level 2 cache or no level 3 cache if valid 2nd level cache.
Instruction trace cache:
	Size: 12K uOps	8-way associative.
L2 unified cache:
	Size: 512KB	Sectored, 8-way associative.
	line size=64 bytes.

Number of reporting banks : 4

Number of extended MC registers : 12


Bank: 0 (0x400)
MC0CTL:    00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000
MC0STATUS: 00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000
MC0ADDR:   00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000

Bank: 1 (0x404)
MC1CTL:    00000000 00000000 00000000 00000000
           00000000 00000011 10000000 00000000
MC1STATUS: 00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000
MC1ADDR:   00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000

Bank: 2 (0x408)
MC2CTL:    00000000 00000000 00000000 00000000
           00000000 00000000 00000000 10000000
MC2STATUS: 00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000
MC2ADDR:   Couldn't read MSR 0x40a

Bank: 3 (0x40c)
MC3CTL:    00000000 00000000 00000000 00000000
           00000000 00000000 00000000 01111110
MC3STATUS: 00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000
MC3ADDR:   00000000 00000000 00000000 00000000
           00000000 00000000 00000000 00000000

Number of logical processors supported within the physical package: 2

Microcode version: 0x0000000000000024

Connector type: Socket478 (PGA478 Socket)

Datasheet: http://developer.intel.com/design/pentium4/datashts/24988703.pdf
	http://developer.intel.com/design/pentium4/datashts/29864304.pdf
Errata: http://developer.intel.com/design/pentium4/specupdt/24919928.pdf

MTRR registers:
MTRRcap (0xfe): 0x0000000000000508
MTRRphysBase0 (0x200): 0x0000000000000006
MTRRphysMask0 (0x201): 0x0000000ff0000800
MTRRphysBase1 (0x202): 0x00000000f8000001
MTRRphysMask1 (0x203): 0x0000000ffc000800
MTRRphysBase2 (0x204): 0x00000000f2000001
MTRRphysMask2 (0x205): 0x0000000ffe000800
MTRRphysBase3 (0x206): 0x0000000000000000
MTRRphysMask3 (0x207): 0x0000000000000000
MTRRphysBase4 (0x208): 0x0000000000000000
MTRRphysMask4 (0x209): 0x0000000000000000
MTRRphysBase5 (0x20a): 0x0000000000000000
MTRRphysMask5 (0x20b): 0x0000000000000000
MTRRphysBase6 (0x20c): 0x0000000000000000
MTRRphysMask6 (0x20d): 0x0000000000000000
MTRRphysBase7 (0x20e): 0x0000000000000000
MTRRphysMask7 (0x20f): 0x0000000000000000
MTRRfix64K_00000 (0x250): 0x0606060606060606
MTRRfix16K_80000 (0x258): 0x0606060606060606
MTRRfix16K_A0000 (0x259): 0x0000000000000000
MTRRfix4K_C8000 (0x269): 0x0505050505050505
MTRRfix4K_D0000 0x26a: 0x0000000000000000
MTRRfix4K_D8000 0x26b: 0x0000000000000000
MTRRfix4K_E0000 0x26c: 0x0505050505050505
MTRRfix4K_E8000 0x26d: 0x0505050505050505
MTRRfix4K_F0000 0x26e: 0x0505050505050505
MTRRfix4K_F8000 0x26f: 0x0505050505050505
MTRRdefType (0x2ff): 0x0000000000000c00


2.8Ghz processor (estimate).

--------------------------------------------------------------------------
