0. old reports waiting for ACK =============================================
+ FEATURE: expose DOTDIR (~/.sch-rnd, as ./configured) in the conf tree in so $(rc.path.user_dotdir) would work [report: Ade]

1. 1.0.0 (Beta) ==========================================================

2. 1.0.1 ==================================================================
- BUG: connect attribute works only on existing ports {des2:55} [report: Majenko]
	- consider making it create ports
		- don't return -1 in std_cschem.c:157 because a second connection in the array is not processed then
	- or if not:
		- remove std_cschem.c:150 because it creates the port
	- also related to TODO#rgc below
		- we shouldn't get errors on bug_files/TODO/rgc1.rs - power rail symbols should probably request the error using an attribute explicitly
- BUG: bug_files/TODO/rtree1.rs: copy the vertical wire and short horizontal wire ("r") from AAA onto BBB grabbing at the junction; the rtree for BBB breaks after the net merge: it jumbs down to some negative coords, enlarging the sheet, making the text object ghost when the bottom left corner is not visible [report: aron]
- FEATURE: "require graphical connection" attribute for gnd and vcc and rail, see TODO#rgc
- BUG: bug_files/TODO/FillBug.rs: symbol's rectangle fill is drawn after some of the text objects, hiding them; comment line 205 to disable the fill; poly fill should be drawn before anything else in a sym [report: Majenko]
	- BUG: the same probably happens outside of symbols, on sheet level as well
- BUG: devmap not found: [report: Majenko]
	- 1. Place a symbol. 2. Make a devmap in ~/.sch-rnd/devmap 3. Add a devmap attribute to the placed symbol pointing to the new file. 4. Look at the message log.
	-> need a rescan?
- BUG: slots identified by alpha (instead of digit) doesn't work [report: Majenko]
- BUG: bug_files/TODO/unl; sch-rnd project.lht; file/project/new unlisted; create local file, it's not added to the project file [report: Igor2]
- BUG: bug_files/TODO/unl; sch-rnd project.lht; file/project/new unlisted; file name "/tmp/new.rs"; new sheet goes into a new, unnamed project [report: aron]
- BUG: boxsym-rnd: edakrill r1159: labels overlap [report: Igor2]
- FEATURE: the integrity check shall verify rtree vs. data tree, that every object is in the rtree and rtree has no ghost objects [report: clarity]
- CLEANUP: split lib_alien's read.c, move out postproc functions to read_postproc.c
- CLEANUP: bug_files/TODO/bbox_flt.patch
	- the idea is that the normal rtree bbox of symbols should not include floaters, but some other things, like sheet extents, should include floaters
	- apply the patch, debug why sheet doesn't grow and auto-normalize doesn't work with io_tinycad (objects not moved to 0;0 on work/alien/tinycad/nkd/4.dsn)
	- turn on the symbol meta layer to see the bbox
	- debug io_tinycad load:
		- search for NKD#1 and NKD#2 in the code
		- easy testing: work/alien/tinycad/nkd/[01234567].dsn (these are the cases one by one, manually copied out from sym_power2)
		- get the lib also calculate the naked bbox for every object (should be in hdr)
		- redraw sym_power2 so that all symbols are within the drawing (half the distance between them)
		- do the same for sym_power3 (that's the show_power=0 variant)
		- ask aron to draw a trace to the left input to all these
- TODO#38: rethink grp-ref-in-grp-ref with child xforms, maybe cache=1 is a bad idea
	- problem: ref1 -> ref2 -> grp -> text; ref2 is floater; if whole ref2 is rotated, we won't update anything in ref1's central xform list
- FEATURE: integrity check messages should contain the name/path of the sheet causing the problem [report: aron]
- BUG: csch_grp_ref_embed(), used in sym loclib paste and right click symbol context menu toref (to loclib) conversion is not undoable [report: Igor2]
- BUG: wirenet name attrib disappears; bug_files/power.rs; box-select the right side net; move the whole thing 1 grid unit to the right; the net name label text becomes a detached group from the rest, the wirenet with wires won't have a name attrib [report: aron]
- io_geda: multiple net= attributes (e.g. in stock 7400) -> should be an array

3. NLnet ==========================================================
- hierarchic design [3]:
	- figure how to handle aux sheets from library (prefix?)
- sim [3]:
	- compiler:
		- verilog-ams wants subcircuit but in a flat multisheet model we don't have that - solution: /work/sim, ex1/ doc
	- cschem model and GUI:
		- no-export mechanism so voltage source is exported only for sim
		- what to put in a symbol (sym model?)
		- simulation parameters:
			- where to put global sim params
			- how to run different simulations in GUI
			- how to run different simulations on export

4. After beta ==========================================================
- a connection object should have x;y displacement for the graphical object to be useful (or is it a grp_ref?); at the moment we are not drawing it at all
- FEATURE: the load sch dialog box file name pattern should maybe ignore sch for gschem and dsn for tinycad
- FEATURE: allow svg schematic export with option of monochrome [report: Erich]
- FEATURE: DRC (requires query() on the abstract model):
	- noslot attribute (e.g. for resistors)
	- figure if fully overlapping ports (or symbols) can be or should be detected (see: two gnd symbols on top of eachother) [report: Erich]
	- it is easy to accidentally add a footprint to a terminal on a symbol instead of the symbol itself. This is not flagged on netlist export. Should it be harder to do this, or maybe a netlist exporter could indicate if footprints associated with terminals in symbols were not included in the export? [report: Erich]
	- accidentally adding a name to a rail exports a connection in the netlist with no associated component. Perhaps this would benefit from some sort of DRC check, like the "footprint attribute put on non-symbol" issue above. [report: Erich]
- FEATURE: text vertical alignment (in design doc and code); same rules as in halign [report: Ade]
- FEATURE: export of the schematic as a pcb-rnd/tedax subcircuit/footprint for placement on the PCB as a graphical element? For simpler circuits, this would be good for "documentation on the silk layer". [report: Erich]
- BUG: copy&paste wirenet line extension merge, see TODO#merge31 in the code [report: Igor2]
- needs librnd4.1 API upgrade:
	- library window "Use selected" should have a tooltip on what exactly it does (for devmap: returns name only, does not update loclib); API: close buttons can't have tooltips [report: aron]

5. Low prio ==========================================================
- BUG: enable multiport_net_merge, then bug_files/multiconn0.rs; move TP2 1k or 2k to the left; more than one connection is created because the vertical ports are overlapping and when the horizontal port is connected, but it figures connections only one by one so it doesn't dare to extend existing connections [report: Igor2]
- BUG: {e t} over a non-dyntext, resize window larger: entry remains small [report: aron]
- FEATURE: bom export; depends on build options (and DNP) [report: Erich]
- FEATURE: view window: open once, single perview widget, copy current zoom+pan, close when parent sheet closed; consider the same for pcb-rnd and camv-rnd [report: Vuokko]
- FEATURE: consider dangling wire end indication (see pool node)
- BUG: wirenet in group should work: load symnet.rs. select terminal and adjacent vertical line using negative selection box; convert selection to symbol. connect test point 1 to wire net. export netlist. do not assume wirenet is directly under the &direct in the tree [report: Erich]
- BUG: back annotation: abstract model: abstract model UUIDs are not implemented, annotation doesn't use them; either figure persistent uuids or use CMRs [report: Igor2]
- BUG: rewrite get_prjname() in dytext render
	- figure the path of the project file
	- project name change runtime (save-as); inalidate text objects (->rtext = NULL using csch_text_dyntext_inval()) to re-render the new name
- OPTIMIZE: do not re-create views multiple times in sch_rnd_prj_conf2prj(): start 'sch-rnd A.rs B.rs' from the same dir [report: Igor2]
- CLEANUP: code dups with pcb-rnd, consider moving some code to src_3rd/rnd_inclib:
	- query
	- propedit
	- undodialog
	- rename csch_ symbols to sch_rnd_ in plugins/
	- act_read
- librnd4.0.0:
	- remove the whole project loading plug io: project files will be handled by librnd
	- once multi is moved over:
		- extend oidpath to generate and accept sheet prefix with $uuid/
		- act_draw should be able to use it as scope
		- act_draw should be able to return oidpath with $uuid/
		- query() should be able to return/convert lists like that for scripting

6. TODO() tags ==========================================================
	- symedit:    needed for symbol editor support
	- bitmap:     needed for bitmap objects
	- fungw:      may need fungw API change
	- multi:      multiple sheet support
	- hierarchic: needed for hierarchic projects
