# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -check-prefix=VI %s

#===------------------------------------------------------------------------===#
# Image load/store
#===------------------------------------------------------------------------===#

# VI: image_load v[0:3], v4, s[8:15] dmask:0xf unorm ; encoding: [0x00,0x1f,0x00,0xf0,0x04,0x00,0x02,0x00]
0x00 0x1f 0x00 0xf0 0x04 0x00 0x02 0x00

# VI: image_load v[0:2], v4, s[8:15] dmask:0xe unorm ; encoding: [0x00,0x1e,0x00,0xf0,0x04,0x00,0x02,0x00]
0x00 0x1e 0x00 0xf0 0x04 0x00 0x02 0x00

# VI: image_load v[0:1], v0, s[0:7] dmask:0x3 unorm ; encoding: [0x00,0x13,0x00,0xf0,0x00,0x00,0x00,0x00]
0x00 0x13 0x00 0xf0 0x00 0x00 0x00 0x00

# VI: image_load v0, v0, s[0:7] dmask:0x1 unorm ; encoding:   [0x00,0x11,0x00,0xf0,0x00,0x00,0x00,0x00]
0x00 0x11 0x00 0xf0 0x00 0x00 0x00 0x00

# VI: image_store v[0:3], v4, s[0:7] dmask:0xf unorm ; encoding: [0x00,0x1f,0x20,0xf0,0x04,0x00,0x00,0x00]
0x00 0x1f 0x20 0xf0 0x04 0x00 0x00 0x00

# VI: image_store v[0:2], v4, s[0:7] dmask:0xe unorm ; encoding: [0x00,0x1e,0x20,0xf0,0x04,0x00,0x00,0x00]
0x00 0x1e 0x20 0xf0 0x04 0x00 0x00 0x00

# VI: image_store v[0:1], v2, s[0:7] dmask:0x3 unorm ; encoding: [0x00,0x13,0x20,0xf0,0x02,0x00,0x00,0x00]
0x00 0x13 0x20 0xf0 0x02 0x00 0x00 0x00

# VI: image_store v0, v1, s[0:7] dmask:0x1 unorm ; encoding: [0x00,0x11,0x20,0xf0,0x01,0x00,0x00,0x00]
0x00 0x11 0x20 0xf0 0x01 0x00 0x00 0x00

# Test dmask == 0
# VI: image_load v0, v4, s[8:15] unorm ; encoding: [0x00,0x10,0x00,0xf0,0x04,0x00,0x02,0x00]
0x00 0x10 0x00 0xf0 0x04 0x00 0x02 0x00

# Test out of bounds register width
# VI: image_load v254, v0, s[0:7] dmask:0x7 unorm ; encoding: [0x00,0x17,0x00,0xf0,0x00,0xfe,0x00,0x00]
0x00 0x17 0x00 0xf0 0x00 0xfe 0x00 0x00

# VI: image_load v255, v0, s[0:7] dmask:0x1 unorm ; encoding: [0x00,0x11,0x00,0xf0,0x00,0xff,0x00,0x00]
0x00 0x11 0x00 0xf0 0x00 0xff 0x00 0x00

# VI: image_load v255, v0, s[0:7] dmask:0x3 unorm ; encoding: [0x00,0x13,0x00,0xf0,0x00,0xff,0x00,0x00]
0x00 0x13 0x00 0xf0 0x00 0xff 0x00 0x00

#===------------------------------------------------------------------------===#
# Image atomics
#===------------------------------------------------------------------------===#

# VI: image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x48,0xf0,0x01,0x05,0x02,0x00]
0x00,0x11,0x48,0xf0,0x01,0x05,0x02,0x00

# VI: image_atomic_add v252, v1, s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x48,0xf0,0x01,0xfc,0x02,0x00]
0x00,0x11,0x48,0xf0,0x01,0xfc,0x02,0x00

# VI: image_atomic_add v5, v255, s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x48,0xf0,0xff,0x05,0x02,0x00]
0x00,0x11,0x48,0xf0,0xff,0x05,0x02,0x00

# VI: image_atomic_add v5, v1, s[92:99] dmask:0x1 unorm ; encoding: [0x00,0x11,0x48,0xf0,0x01,0x05,0x17,0x00]
0x00,0x11,0x48,0xf0,0x01,0x05,0x17,0x00

# VI: image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x48,0xf0,0x01,0x05,0x02,0x00]
0x00,0x31,0x48,0xf0,0x01,0x05,0x02,0x00

# VI: image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm slc ; encoding: [0x00,0x11,0x48,0xf2,0x01,0x05,0x02,0x00]
0x00,0x11,0x48,0xf2,0x01,0x05,0x02,0x00

# VI: image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm lwe ; encoding: [0x00,0x11,0x4a,0xf0,0x01,0x05,0x02,0x00]
0x00,0x11,0x4a,0xf0,0x01,0x05,0x02,0x00

# VI: image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm da ; encoding: [0x00,0x51,0x48,0xf0,0x01,0x05,0x02,0x00]
0x00,0x51,0x48,0xf0,0x01,0x05,0x02,0x00

# VI: image_atomic_add v[5:6], v1, s[8:15] dmask:0x3 unorm ; encoding: [0x00,0x13,0x48,0xf0,0x01,0x05,0x02,0x00]
0x00,0x13,0x48,0xf0,0x01,0x05,0x02,0x00

# VI: image_atomic_cmpswap v[5:6], v1, s[8:15] dmask:0x3 unorm ; encoding: [0x00,0x13,0x44,0xf0,0x01,0x05,0x02,0x00]
0x00,0x13,0x44,0xf0,0x01,0x05,0x02,0x00

# VI: image_atomic_cmpswap v[5:8], v1, s[8:15] dmask:0xf unorm ; encoding: [0x00,0x1f,0x44,0xf0,0x01,0x05,0x02,0x00]
0x00,0x1f,0x44,0xf0,0x01,0x05,0x02,0x00

#===------------------------------------------------------------------------===#
# Invalid image atomics (incorrect dmask value).
# Disassembler may produce a partially incorrect instruction but should not fail.
#===------------------------------------------------------------------------===#

# VI: image_atomic_add v5, v1, s[8:15] dmask:0x2 unorm ; encoding: [0x00,0x12,0x48,0xf0,0x01,0x05,0x02,0x00]
0x00,0x12,0x48,0xf0,0x01,0x05,0x02,0x00

# VI: image_atomic_add v5, v1, s[8:15] dmask:0x7 unorm ; encoding: [0x00,0x17,0x48,0xf0,0x01,0x05,0x02,0x00]
0x00,0x17,0x48,0xf0,0x01,0x05,0x02,0x00

# VI: image_atomic_add v5, v1, s[8:15] dmask:0xf unorm ; encoding: [0x00,0x1f,0x48,0xf0,0x01,0x05,0x02,0x00]
0x00,0x1f,0x48,0xf0,0x01,0x05,0x02,0x00

# VI: image_atomic_cmpswap v[5:6], v1, s[8:15] unorm ; encoding: [0x00,0x10,0x44,0xf0,0x01,0x05,0x02,0x00]
0x00,0x10,0x44,0xf0,0x01,0x05,0x02,0x00

# VI: image_atomic_cmpswap v[5:6], v1, s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x44,0xf0,0x01,0x05,0x02,0x00]
0x00,0x11,0x44,0xf0,0x01,0x05,0x02,0x00

# VI: image_atomic_cmpswap v[5:6], v1, s[8:15] dmask:0xe unorm ; encoding: [0x00,0x1e,0x44,0xf0,0x01,0x05,0x02,0x00]
0x00,0x1e,0x44,0xf0,0x01,0x05,0x02,0x00
